申请职位
发布时间:2021-06-08
IC前端工程师
全职 研发类
北京
职位描述

岗位职责:

Key Responsibilities:

1.IC Block design for all frontend phase.

2.IC chip level design for all fontend phase

Architecture define;RTL implementation;Analysis and Optimization for performance;Analysis and Optimization for power;Analysis and Optimization for timing;Design flow: lint/synthesis/sta/formal check;Silicon debugging.


任职条件:

Qualifications:

1.BS / MS with 5+ years of experience in ASIC or FPGA design.

2.Experience with CPU related IPs design are highly desirable.

3.Experience as design lead for complex or high speed IPs.

4.Experience with all phases of frontend architecture, design and validation.

5.RTL Coding, Design Reviews, SYN, CDC, FEV, DFT insertion, ATPG analysis.

6.Demonstrated work experience with timing Analysis, Area and Power optimizations, Performance Analysis, Debug ability and Security analysis, ECOs, and Post-Silicon Debug.

7.Excellent knowledge of Verilog and popular EDA simulation & implementation tools.

8.Good experience in scripting languages like Perl, Unix shell or similar languages.

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